![]() Icarus Verilog is a Verilog simulation and synthesis tool. A test environment that is built for a commercial simulator that only a limited number of people have access to makes verification more complicated. An IP that has readily available scripts for an open source HDL simulator makes it easier for an other person to verify and possibly update that particular core. The use of such tools makes it easier to collaborate at the opencores site. There are plenty of good EDA tools that are open source available. A lot more steps are needed to verify the cores and to ensure they can be synthesized to different FPGA architectures and various standard cell libraries. Designing IP cores, is unfortunately not as simple as writing a C program. ![]() OpenCores is the world largest community focusing on open source development targeted for hardware. ![]()
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